1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a nonvolatile memory apparatus, a repair circuit for the same, and a method for reading code addressable memory (CAM) data.
2. Related Art
A nonvolatile memory apparatus represented by a flash memory apparatus has advantages in that it may freely record and erase data and conserve data stored therein even though power supply is cut off. Thus, the nonvolatile memory apparatus has been recently adopted as a storage medium for a variety of digital devices.
Such a nonvolatile memory apparatus adopts a repair method in which main memory cells and redundancy memory cells are used together, in order to improve the yield. In the repair method, when a defect exists in a main memory cell, the main memory cell is replaced by a redundancy memory cell. In order to repair a memory cell in which a defect occurs, repair address information, column address information in which the memory cell having a defect is included, input/output port address information and so on need to be stored in a separate storage unit.
Conventionally, repair information has been stored by using a fuse. In such a repair method using a fuse, the repair information is stored by fuse cutting, before a nonvolatile memory apparatus is packaged. Therefore, after the packaging is completed, the repair information cannot be updated.
Recently, repair information has been stored in a CAM. In such a repair method using a CAM, a specific block of a memory cell array including a plurality of blocks is allocated as a CAM cell block to store repair address information or option information as CAM data.
CAM data includes CAM setting data CAMDATA_LOG such as internal bias information or internal logic setting information, redundancy address information CAMDATA_RED, and bad block information CAMDATA_BAD. Such CAM data is read from a corresponding storage area at every normal operation of a nonvolatile memory and stored in a latch of a repair circuit.
FIG. 1 is a timing diagram explaining a conventional method for reading CAM data.
As a normal operation of a nonvolatile memory apparatus starts, a log data load signal CAMLOG_LOAD is asserted, and thus CAM log data CAMDATA_LOG is stored in a latch according to a designated address. When the storing of the CAM log data CAMDATA_LOG is completed, a redundancy address information load signal CAMRED_LOG is asserted to store redundancy address information CAMDATA_RED in a designated address area of the latch. Then, when a bad block information load signal CAMBAD_LOAD is asserted, the CAM bad block information CAMDATA_BAD is stored in a designated address area of the latch.
In FIG. 1, CAM_BUSY represents a CAM data read enable signal outputted from a controller, and CAMADD represents address information for storing the respective CAM data.
As such, since the respective CAM data are sequentially read and stored in the latch, a considerable amount of time is required for reading the CAM data at the initial stage of a normal operation.
Furthermore, since the operation of reading the CAM data and storing the read CAM data in the latch is performed whenever a normal operation starts, the operation may serve as a factor which determines the operation speed of the nonvolatile memory apparatus. Accordingly, there is a demand for a method capable of reducing the operation time.